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ISL6590
Data Sheet April 2003 FN9061
Digital Multi-Phase PWM Controller for Core-Voltage Regulation
Processors that operate above a GHz require fast, intelligent power systems. The Intersil ISL6590 controller offers intelligent digital, multi-phase control that provides high bandwidth, optimal control frequency response, noise immunity and active transient response control algorithms. The design is fully scalable for controlling up to six phases, each featuring the Intersil ISL6580 intelligent power stage. The user can configure and monitor the power system via the Asynchronous Serial Interface (ASI). The ISL6590 controller flexibility can be extended with the addition of an external EEPROM for updating key circuit operating parameters in the control loop and overall system design. The digital architecture reduces the design time for engineers with the use of our software. The software allows the designer the freedom to choose output stage components and still achieve optimized system performance. The ISL6590 digital controller communicates with the ISL6580 integrated power stages via 100% digital signaling. Serial communication allows for separation of the controller and the power stage, providing placement and layout freedom to the power stage. The digital controller implements phase balancing to ensure even distribution of phase currents. The ISL6590 controller configures the ISL6580 power stage current limit, VID reference, nonoverlap period, Active Transient Response (ATR) trigger levels and maximum temperature limit. The digital controller also monitors the ISL6580 power stage peak currents, overtemperature fault, input under voltage, output over/under voltage to ensure proper operation of the power supply.
Features
* Open Architecture features software programmable control loop compensation enabling optimal system performance - User accessible asynchronous serial interface * Intel VR10 - 6-bit Dynamic VIDTM - Output voltage regulation range of 0.8375V to 1.600Vdc * 250kHz to 1MHz switching frequency * 100% digital control and signaling * Active Transient Response (ATR) control algorithms for minimized voltage droop and overshoot * Controls up to six ISL6580 intelligent power stages (20A per phase, 120A total system current) * Programmable Adaptive voltage positioning (AVP) load line * Configurable control loop parameters (with optional external EEPROM) * Programmable MOSFET dead time control * High speed voltage and current control loops * PWRGD and OUTEN * Serial interface to ISL6580 power stages for system monitoring and configuration * 64 Ld 9x9 QFN package * QFN Package Option - QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile.
Pinout
ISL6590 (QFN) TOP VIEW
PLL_FILTER PLL_ANALOG_VDD PLL_ANALOG_VSS PLL_DIGITAL_VDD PLL_DIGITAL_VSS OSC_IN OSC_OUT VDD_CORE ARX ATX VDD_IO SCLK SDATA TEST4 TEST3 ATRH
Ordering Information
PART NUMBER ISL6590DR
TEST 2 ATRL SOC ERR VDD_IO SYS_CLK VDD_IO NC NC VDD_CORE NC NC IDIG6 PWM6 NDRIVE6 TEST1
TEMP. (oC) 0 to 85
PACKAGE
PKG. NO.
64 Ld 9x9 QFN L64.9x9-S
OUTEN VID [0] VID [1] VID [2] VID [3] VID [4] VID [5] VDD_CORE PWRGD VDD_IO MCLK MDO MDI MCS NDRIVE1 PWM1
64 01
49 48
16 17 IDIG1 NDRIVE2 PWM2 IDIG2 VDD_CORE NDRIVE3 PWM3 IDIG3 VDD_IO NDRIVE4 PWM4 IDIG4
33 32 EXT_RESETB NDRIVE5 PWM5 IDIG5
1
CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Dynamic VIDTM is a trademark of Intersil Americas Inc.
ISL6590 Typical Application Circuit
3.3 V 5-12 V 12 V 3.3 V 1.8 V 2.5 V
VDD VDRIVE VCC
VDD_IO
VDD_CORE
VREF ATRH ATRL ERR SOC SCLK SDATA CLK
V SENP VSENN ISENSE VSW NGATE
VID[0:5] PWRGD OUTEN
ERR SOC SCLK SDATA SYSCLK PWM IDIG NDRIVE
ISL6580
Vout
PWM IDIG NDRIVE
PGND GND
REGULATION CHANNEL
ARX ATX
Vout RTN
ISL6590
3.3 V
5-12 V 12 V
VDD
VDRIVEVCC
ATRH ATRL
VREF ATRH ATRL ERR SOC SCLK SDATA CLK
V SENP VSENN ISENSE VSW NGATE
ISL6580
OSC_IN OSC_OUT
PWM IDIG NDRIVE TEST1 TEST2 TEST3 TEST4
PWM IDIG NDRIVE
PGND GND 5-12 V 12 V
ATR CHANNEL
3.3 V
VDD
VDRIVE VCC
MDO
EEPROM
VREF ATRH ATRL ERR SOC SCLK SDATA CLK PWM IDIG NDRIVE
V SENP VSENN ISENSE VSW NGATE
MDI MCS MCLK
ISL6580
PWM IDIG NDRIVE
PGND GND
UV/OV CHANNEL
GND
CONTROLLER INTERFACE BUS
2
ISL6590
Absolute Maximum Ratings
Supply Voltage (VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.63V (VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.98V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Information
Thermal Resistance JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . JA-0 LFPM AIR . . . . . . . . . . . . . . . . . . . JA-100 LFPM AIR . . . . . . . . . . . . . . . . . JA-200 LFPM AIR . . . . . . . . . . . . . . . . . JA-400 LFPM AIR . . . . . . . . . . . . . . . . . JB . . . . . . . . . . . . . . . . . . . . . . . . . . . . (oC/W) 3 29.0 26.6 25.0 23.2 8
Recommended Operating Conditions
Supply Voltage (VDD_IO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V 5% (VDD_Core) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V 5% (Analog PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V 5% (Digital PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V 5% Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .125oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
CAUTION: Stress above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a "High Effective" Thermal Conductivity Board with "Direct Attach" features. (See Tech Brief TB379 for details.)
Electrical Specifications
PARAMETER INPUTS Outen, VID[0:5], VIH Outen, VID[0:-5], VIL
Operating Conditions: VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
3.3V no internal pull-up/down resistors 3.3V no internal pull-up/down resistors 3.3V internal pull-down resistor 3.3V internal pull-down resistor 3.3V internal pull-up resistor 3.3V internal pull-up resistor 3.3V internal pull-up resistor 3.3V internal pull-up resistor No internal pull-up/down resistors No internal pull-up/down resistors
0.8 2.0 2.0 2.0 2.0 -
-
0.4 0.8 0.8 0.8 0.8
V V V V V V V V V V
MDI, IDIG[1-6], ATRL, ATRH, SOC, ERR VIH MDI, IDIG[1-6], ATRL, ATRH, SOC, ERR VIL EXT_RESETB, VIH EXT_RESETB, VIL ARX, VIH ARX, VIL OSC_IN, VIH OSC_IN, VIL OUTPUTS MCLK, MDO, MCS, NDRIVE[0:5], PWM[0:5], ATX, VOH MCLK, MDO, MCS, NDRIVE[0:5], PWM[0:5], ATX, VOL SYS_CLK, VOH SYS_CLK, VOL SCLK, VOH SCLK, VOL SDATA, VOH SDATA, VOL SDATA, VIH SDATA, VIL PWRGD, VOH PWRGD, VOL OSC_OUT, VOH OSC_OUT, VOL
No internal pull-up/down resistors, 8mA drive No internal pull-up/down resistors, 8mA drive No internal pull-up/down resistors, 20mA drive No internal pull-up/down resistors, 20mA drive No internal pull-up/down resistors, 16mA drive No internal pull-up/down resistors, 16mA drive 3.3V pull-up resistor, 16mA drive 3.3V pull-up resistor, 16mA drive 3.3V pull-up resistor 3.3V pull-up resistor Open drain, 6mA drive Open drain, 6mA drive No internal pull-up/down resistors, 10mA drive No internal pull-up/down resistors, 10mA drive
2.4 2.4 2.4 2.4 2.0 2.4 2.4 -
-
0.4 0.4 0.4 0.4 0.8 0.4 0.4
V V V V V V V V V V V V V V
3
ISL6590
Electrical Specifications
PARAMETER POWER-ON RESET AND ENABLE POR Threshold Vddio Rising Vddio Falling Vddcore Rising Vddcore Falling OUTEN Threshold OUTEN Rising OUTEN Falling OSCILLATOR Adjustment Range Max Duty Cycle NOTE: 1. Reserved for note. 0.250 24 TBD 1 MHz % 1.4 0.7 0.71 0.64 2.55 1.4 V V V V V V Operating Conditions: VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25oC, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN TYP MAX UNITS
Block Diagram
Ext_Reset
POR
ATX ARX
Asynchronous Serial Interface Memory Bus MUX
Feedback Control
PWM [6:1]
PWM Driver
NDRIVE [6:1] ATRH ATRL
OUTEN PWRGD VID[5:0]
State Control and Fault Monitor
Current Loop Voltage Loop
IDIG[6:1]
MDI MCLK MCS MDO
Non-Volatile SPI EEPOM Interface
Control/ Status Registers
AVP
SOC ERR
OSC_OUT OSC_IN PLL_FILTER
Clock Distribution
State Machine
MHz Memory Mapped Registers
Backside Serial Bus
SCLK SDATA
SYS_CLK
FIGURE 1. ISL6590 BLOCK DIAGRAM
4
ISL6590 Pin Descriptions
PIN NO. 1 2-7 8, 21, 39, 57 9 10, 25, 42, 44, 54 11 12 13 14 15, 18, 22, 26, 30, 34 16, 19, 23, 27, 31, 35 17, 20, 24, 28, 32, 36 PIN NAME OUTEN VID[0:5] VDD_CORE PWRGD VDD_IO MCLK MDO MDI MCS NDRIVE[1:6] PWM[1:6]
IDIG[1:6]
TYPE Input Input Power Output Power Output Output Input Output Output Output Input
PIN DESCRIPTION Output enable high input signal used to command the regulator on and a low input signal turns the regulator off. Voltage identification (6 bit). Programs Vout regulation voltage. IC internal core supply voltage (1.8 VDC logic). Power Good high output signal to indicate the regulator output voltage is within the specified range. A low signal indicates the voltage is not within range. IC I/O input supply voltage (3.3 VDC logic). EEPROM external memory clock, data is clocked out of the IC on the rising edge and data is clocked into the ISL6580 IC on the falling edge. Compliant with SPITM EEPROMs. EEPROM external memory data output. Compliant with SPI EEPROMs. EEPROM external memory data input. Compliant with SPI EEPROMs. EEPROM external memory chip select (Active low). Compliant with SPI EEPROMs. Low side drive signal used to initiate the ISL6580 to turn on the LSFET. PWM performs pulse width modulation which is used to turn on the ISL6580's power devices. Current A/D data serial 7-bit digital word (MSB first). The first bit is a start bit (Start = 1). The remaining 6 bits represent the sampled peak current in the drain of the particular ISL6580 P-Channel HSFET. (IDIG word transmission is triggered by the falling edge of the PWM signal.) IDIG is an input that is received at SYSCLK/2, normally 66.6MHz. Voltage identification (6 bit). Programs Vout regulation voltage. Test pins for part evaluation These pins have not been bonded out. System clock which runs at a 133.3MHz rate used to clock the ISL6580. This is generated by the internal PLL circuit to create a 4x frequency multiply of the OSC_IN frequency. Serial data transmitted at a 66MHz (or SYSCLK/2) rate. This 6 bit voltage error is feedback into the control loop and used to regulate the output voltage. Start of Conversion signal initiated by the ISL6580's Voltage A/D to create the ERR signal. Active Transient Response Low input signal from the ISL6580 indicating a voltage overshoot on the converter output. Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the converter output. Controller serial interface for communication, monitoring, and configuration data between the ISL6580 and ISL6590 controller. Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the Backside serial bus. Asynchronous Serial Interface Transmit Asynchronous Serial Interface Receive Only used if part is using a crystal to generate the system clock. Requires a 33.33MHz oscillator or crystal which is used to generate system clock. Digital Ground for the 4X clock multiplier PLL. Test mode to bypass PLL input to core. 1.8V power supply for the 4X clock multiplier PLL clock tree driver (1.8 VDC logic). Analog Ground for the 4X clock multiplier PLL. 1.8V power supply for the 4X clock multiplier PLL (1.8 VDC logic).
29 33, 48, 50, 51 37, 38, 40, 41 43 45 46 47 49 52 53 55 56 58 59 60 61 62 63 64 65
EXT_Reset TEST[1:4] NC SYSCLK ERR SOC ATRL ATRH SDATA SCLK ATX ARX OSC_OUT OSC_IN PLL_DIG_VSS PLL Bypass PLL_DIG_VDD PLL_ANA_VSS PLL_ANA_VDD PLL_Filter GND
Input Output N/A Input/Output Input Input Input Input Input/Output Output Output Input Output Input Ground Input Power Ground Power
Analog Input Filter cap for PLL. Ground Paddle IC Ground
5
ISL6590 General Description
The ISL6590 is a multiphase digital controller optimized for microprocessor core voltage generation in the 0.8375Vdc 1.600Vdc output range and high current loading up to 150A with a 12Vdc input. It is intended to be used as a chipset with multiple ISL6580 power stages. The current per stage is up to 25A and the switching frequency can operate from 250kHz to 1MHz. The adaptability of having a digital controller with a serial data bus to the power stages means that the control algorithms can be adjusted with software instead of having to make hardware or board changes. All of the features of the ISL6590 are available in applications that require 3-6 phases of PWM (Pulse-Width Modulation) core voltage regulation. For more information on the power stage, consult the ISL6580 data sheet. Each of the ISL6580s contains a 6-bit voltage ADC that can be used to measure the difference between the core voltage at the output and a reference voltage that is set by the VID information. Even though each ISL6580 has the voltage ADC, only one of them is required to use it. When a large change in current occurs at the output load, a large voltage transient also occurs. The ATRH and ATRL levels are designed to trigger a temporary mode in which the PWM generator aligns all phases or removes all phases in order to quickly raise or lower the output voltage.
Controller Memory
The internal volatile memory provides control and status registers which are reset to default states on each power up. These registers can be altered with commands from the ASI, the State Control and Fault Monitors, or the Serial Interface with the ISL6580 Power ICs.
Block Diagram Overview
The ISL6590 contains functionality to control up to 6 power stages with PWM core voltage regulation. The blocks described follow the block diagram shown in Figure 1. For additional help it would be useful to reference the block diagram of the ISL6580, which is located in the ISL6580 data sheet.
EEPROM Interface (MCS, MCLK, MDI, MDO)
An external EEPROM (non-volatile memory) can be used to write custom information to the volatile memory. The nonvolatile memory can be modified via the ASI. The EEPROM contains configuration values for a given design. The ISL6590 uses the standard Serial Peripheral Interface (SPITM) serial protocol for this memory. The EEPROM must be at least a 2K byte memory. Larger memory can be used without problems, however the ISL6590 will utilize only 2K bytes.
Asynchronous Serial Interface (ASI) (ATX, ARX)
This 2-wire serial data host interface is designed to transfer command information from the designers PC to the controller, such as adjustments to register settings. The ASI is used during the design process to configure and test your power supply settings. It allows the designer to change loop coefficients to achieve the best response for their system design. This serial bus runs at 115K baud rate to interface with a host computer during testing.
Clock Distribution (OSC_IN, OSC_OUT)
The clock distribution block creates the internal system clock from an external clock source such as a crystal oscillator. It performs a 4x frequency multiplication of the external clock frequency. The maximum clock input is 33.33MHz for an IC sample rate of 133.3MHz. It generates the read/write clock for the ASI. The system clock is provided to the ISL6580s via the SYS_CLK pin.
Backside Serial Bus (BSB) (SDATA, SCLK)
The backside serial bus is a 2-wire communication between the ISL6590 controller and the ISL6580 power ICs used for transfer of control and status information. This bus is critical for proper operation of the system, any miscommunications will cause a bus error between the controller and power stages and shutdown the power supply. A bus error can be caused by poor routing of those lines or by a failed ISL6580.
State Control and Fault Monitoring (OUTEN, VID[5:0], PWRGD)
Implements control of the power system state and processes fault information from the ISL6580 Power IC. All fault detection within the system is accomplished within each individual ISL6580 and is communicated to the ISL6590 via the Backside Serial Interface. ISL6590 detects the fault through constant polling of the ISL6580 fault registers and responds by tristating the outputs or shutting down the system which then requires a power cycle and initiates a softstart sequence.
Feedback (PWM, NDRIVE, ATR, IDIG, SOC, ERR)
The feedback control block implements the loop compensation, hysteretic control, and switch driver. Defaults for the loop compensation coefficients are retained in the memory block. If the default values need to be optimized, they can be adjusted using the ASI. The PWM generator that drives NDRIVE and PWM derives its waveform from a current balancing circuit that balances the current to each phase. The current balancing circuit requires information about the amount of current each phase is supporting. This information is obtained using the 6-bit current ADC in each ISL6580.
Memory Bus Multiplexer
Controls the priority of data transfer to the volatile memory (control registers) from both the ASI and the state control and fault monitoring. The state control and fault monitoring is given priority over the ASI.
6
ISL6590
AVP0 AVP PID
VERR
6-BIT OFFSET BINARY
(FROM ERR SIGNAL - ISL6580 VOLTAGE ADC)
IDIG1 IDIG2 IDIG3 IDIG4 IDIG5 IDIG6
6-BIT SERIAL
PIDOUT IAVG
CURRENT AVERAGING
PWM[6:1]
CURRENT BALANCING
PWM GENERATOR
PARALLEL LINES
NDRIVE[6:1] (TO ISL6580s)
IERR ISHARE CURRENT SHARE ATRH ATRH ATRL
(FROM ISL6580 ATRH AND ATRL SIGNALS)
FLASH LOGIC
ATRL
FIGURE 2. FEEDBACK CONTROL DIAGRAM
Block Diagram Details
Feedback Control
At a minimum, there must be three ISL6580s available to implement the following modes. 1. Regulation Mode (Voltage ADC) 2. Voltage Transient Mode (ATR Window Comparator) 3. Over/Under Voltage Mode (O/U Voltage Comparator) Additional phases 4-6 are in normal conversion mode. Located in the Feedback Control section of the ISL6590 is an interface to the feedback information collected and delivered by the analog ISL6580 power stages. To understand the functionality of the ISL6590 feedback algorithms, key blocks of the ISL6580 must be understood, such as the ADC converters and the window comparator.
oscillator rate. The 6-bit current ADC is a successive approximation converter, requiring one clock per bit, for a total of 6 clocks. Another clock cycle is for transferring data to the serial register. Since the PWM and SYSCLK may not be phase related, one extra clock cycle may be required depending on the alignment. It is not possible to predict when the serial data will begin to transfer on the IDIG bus, so a start bit is used to notify the ISL6590 that data is coming. The start bit is followed by the six data bits in descending order from the MSB. A bit is transferred every two SYSCLK cycles. Since the PWM signal is used as the start of conversion signal, a significant glitch on the PWM signal during the conversion or data transfer will initiate a new conversion and abort the present conversion. The ISL6590 uses the serial current information on the IDIG bus to calculate the average of all the phases, compare it to the current of each phase, and balance the phases by adjusting each PWM and NDRIVE signal as necessary. Because the start of conversion is dictated by the falling edge of the PWM signal, the effective sample rate of the current information is the PWM rate (typ<1MHz), even though each bit is converted and transferred at SYSCLK/2 = 66.6MHz. All ISL6580s will return IDIG information, regardless of their mode.
6-bit Current ADC (ISL6580)
A current ADC (Analog-to-Digital Converter) located in each ISL6580 measures, converts, and transmits that driver's current back to the ISL6590 serially via the IDIG[6:1] bus. The start of conversion is initiated on the falling edge of the PWM input signal at the ISL6580 and the conversion takes about 8 SYSCLK cycles. The SYSCLK signal is provided by the ISL6590 to the ISL6580 and is equal to 4x the crystal
7
ISL6590
6-bit Voltage ADC (ISL6580)
Each of the ISL6580s contain a 6-bit voltage ADC that can be used to measure the difference between the core voltage at the output and a reference voltage that is set by the VID information. The VID is sent to the designated ISL6580 via the backside serial bus from the ISL6590 prior to soft start. The voltage difference measured is sent via the ERR signal serially to the ISL6590. Even though each ISL6580 has the voltage ADC, only one of them is required to use it. This mode is called the Regulation Mode. The conversion is initiated with the SOC (Start Of Conversion) signal from the ISL6580 pulsing high for two SYSCLK cycles. After another two SYSCLK cycles, the 6 bits of data are shifted out of the ISL6580 on the ERR signal, one bit every two SYSCLK cycles, starting with the MSB. Because the ADC uses a successive approximation architecture, every two SYSCLK cycles converts one bit, for a total of 12 SYSCLK cycles to make the 6-bit conversion. With a 133.3MHz SYSCLK, 66.6MHz is the sample rate per bit of the ADC and is also the serial data rate of the ERR0 signal. However, since the SOC signal initiates the sampling process, the effective overall sample rate of the voltage measuring system is equal to the SOC rate. removes all phases in order to quickly raise or lower the output voltage. The event is short-lived and the controller quickly returns to normal operation, but the result is an instantaneous boost or reduction in output voltage to keep the transient event within the required regulation window. An ATR window comparator located in the designated ISL6580 generates the ATRH or ATRL indicator signals when the event occurs. The ATRH and ATRL trip levels are offsets from the VID voltage and are set in ISL6590 register 0883h, each with a 4-bit word. The ATRH, ATRL, and VID values from the ISL6590 memory are sent to the designated ISL6580's registers via the BSB prior to soft start. In the ISL6580, these are added or subtracted from the VID target value with 7.5mV LSB resolution to set the trip levels. Whereas AVP is performed with slight, tightly controlled modifications to the PWM duty cycle in the ISL6590 using sampled current data from each phase, ATR is performed with preset values and trips a comparator in a single ISL6580. The ISL6580 ATRH or ATRL signals immediately tell the PWM generator in the ISL6590 to enter the ATR mode. For this reason, the ATR mode is able to react much quicker than the sample rate derived AVP.
MAX=VID ATRL PAVP ILOAD=MIN
Window Comparator (ISL6580)
Each ISL6580 contains a window comparator. At least two ISL6580s must be configured to use it. One is configured with comparator trip levels for Transient Voltage Mode (ATR described below) and the other for Over/Under Voltage Mode which responds via the fault registers and is described in detail under Fault Processing.
PVID
Adaptive Voltage Positioning (AVP)
The Adaptive Voltage Positioning section of the ISL6590 takes the average current of all the active ISL6580 channels and passes it through an AVP gain factor and a low pass filter. The AVP gain factor sets the slope of the load line so that the voltage at high current loading is intentionally less than the voltage at small current loading. The output of the low pass filter is subtracted from the ADC voltage error (ERR signal) to adjust the operating voltage position. The AVP value is modified in the digital compensation block with the coefficients stored in the ISL6590 memory. The resulting modified output is sent to the PWM generator to adjust the target output voltage for all phases with a voltage offset from the nominal VID so that current and voltage transients can better be accommodated.
NAVP ATRH MIN
ILOAD=MAX
FIGURE 3. ADAPTIVE VOLTAGE POSITIONING AND ACTIVE TRANSIENT RESPONSE TRIP LEVELS
Active Transient Response (ATR)
Voltage Transient Mode must be performed by one ISL6580 in the system (but not one already processing another mode). It is done by using the ATR signals between the ISL6580 and ISL6590. When a large change in current occurs at the load, a large voltage transient also occurs. The ATRH and ATRL levels are designed to trigger a temporary mode in which the PWM generator aligns all phases or 8
ISL6590
VID Map
TABLE 1. VOLTAGE IDENTIFICATION (VID) VOUT (V) 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 OFF OFF 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VOUT (V) 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
host interface control of VID requires that a separate register is needed for the value of the external VID input pins. This is needed to separately track changes to the VID set by the host interface and the VID set from the external pins. The same method of output voltage stepping that is used in the Soft Start process is also applied to dynamic VID changes.
Custom VID
The ISL6590 has additional registers for a custom VID table to be created and stored in memory locations 0940-097F.
VID
Control of the output voltage of the regulator is set from the external six bit VID [5:0] input pins. After power-up, the VID inputs are sampled and this value is used as the final output voltage for the Soft Start process. After Soft Start is complete, the internal VID setting may be changed by modifying the external six bit VID [5:0] input pins or via the host interface write to the internal VID register. To allow for 9
1.5500 1.5625 1.5750 1.5875 1.6000
ISL6590
PID
Feedback Control PID block not only performs each of the basic Proportional, Integral, and Differential compensation components, it also includes a Low Pass Filter (LPF) to help reduce high frequency noise and a transient recovery path to help transient event. The coefficients used in the PID portion are Kp, Kd, and Ki. The coefficients used in the LPF are Kfp and Kfd. The calculations in the transient path take the differential AVP output (DAVPout), gained up by Kdf, and then added to the integral path accumulator. The input to the Low pass filter is the adjusted Verr by AVP output. The coefficients for the PID block are stored in modifiable registers in the Controller Memory Map. In order to put a cap on PID output, the Duty_limit term from the memory map is used to saturate the output of the PID block. Controller specific serial interface commands are restricted to reads and writes of the controller memory map. Details are provided in Tables 2-5.
TABLE 2. ASYNCHRONOUS SERIAL INTERFACE CONTROLLER SPECIFIC COMMANDS COMMAND CODE NAME (8 BITS) Read_Byte Write_Byte 00h 01h DESCRIPTION Reads 1 byte at starting address Writes 1 byte at starting address
02h-FFh Reserved TABLE 3. ASYNCHRONOUS SERIAL INTERFACE ERROR CODES COMMAND CODE NAME (8 BITS) No Error 00h 01h No Error Bus Error DESCRIPTION
Current Balancing
This block adjusts each individual channel current, I1-6, by comparing it with the average current, IAV, of all the active channels. The difference between each channel current and the average current passes through a low pass filter and a shift operation to suppress it before it is added to PID output. IERR is an input from the Current Sharing block (not implemented) and represents a difference between the local module's average current and the average currents of all other modules in the system.
Bus Error
02h-FFh Reserved TABLE 4. ASYNCHRONOUS SERIAL INTERFACE READ_BYTE COMMAND FORMAT DATA BYTE DESCRIPTION (FIRST TO LAST) Address (LSB) Address (MSB) Error Read data (0 bytes if error) LENGTH (BYTES) 1 1 1 1 DIRECTION In In Out Out
PWM Generator
The PWM generator delivers 1-6 complementary high side (PWM) and low side (NDRIVE) outputs to each of the ISL6580 power stage's inputs. A high state on the PWM signal enables the high side integrated P-channel MOSFET of each ISL6580. The low side drive signal is a complementary, non-overlapped version of the PWM signal. The rising edge of each PWM phase is evenly distributed over the switching period. Prior to each PWM output, the generator samples the PID output value and generates a pulse that is proportional to the sampled value. A high level on the OUTEN input signal enables the PWM generator. The PWRGD output signal denotes that the output is regulated within the specified limits. If OUTEN is low or a major fault occurs, PWRGD will be low.
TABLE 5. ASYNCHRONOUS SERIAL INTERFACE WRITE_BYTE COMMAND FORMAT DATA BYTE DESCRIPTION (FIRST TO LAST) Address (LSB) Address (MSB) Write data Error LENGTH (BYTES) 1 1 1 1 DIRECTION In In In Out
EEPROM Operation
After the Controller powers up, the SPI Serial EEPROM interface is polled to see if a memory device is connected. This polling is performed by doing a SPI Memory Write Enable (WREN) command and then doing a Read Status Register (RDSR) to see if the Write Enable bit is set correctly. If an external SPI Serial EEPROM is connected to the controller, the Non-Volatile Memory block asserts an EXTMEM bit in the Memory Status Register. If the NVMEMCODE check passes, all non-volatile memory locations in the Controller Memory Map are read from the serial memory and loaded into the local register copies in the Controller. Once the startup checks and configuration loading (if possible) are complete, SPI_READY bit is set in
Asynchronous Serial Interface Details
Writes to the control registers from the ASI are second priority to the fault and state monitoring writes to the control registers. The priority is handled by the Memory Bus Multiplexer. The ASI functions at 115.2 kbits/second with a 50ms inter-byte time-out and reset. The ASI waits for command bytes after reset. The serial data is constructed with a start bit, eight data bits, and a stop bit. Parity is not supported.
10
ISL6590
the status register which then allows accesses to the NonVolatile Memory map.
ISL6590 Data Write Timing
Tp
SCLK
tDSU t DH t KH tSPH
SDATA
FIGURE 6. ISL6590 DATA WRITE TIMING
TABLE 8. DATA WRITE TIMING FIGURE 4. EEPROM DATA READ TIMING TABLE 6. EEPROM DATA READ TIMING TIMING NAME Data Setup Data Hold PARAMETER tDSU tDH MIN 20 20 UNITS ns ns TIMING NAME Data Setup Data Hold Kick Hold Stop Hold SCLK Period PARAMETER tDSU tDH tKH tSPH tp TYPICAL 45 15 15 15 62.5 UNITS ns ns ns ns ns
ISL6590 Data Read Timing
FIGURE 7. DATA READ TIMING
TABLE 9. DATA READ TIMING FIGURE 5. EEPROM DATA WRITE TIMING TABLE 7. EEPROM TIMING TIMING NAME CS to MCLK delay Data Setup Data Hold Clock Period MCLK to CS delay PARAMETER tCSSU tDSU tDH tP tCSH TYPICAL 480 240 240 480 720 UNITS ns ns ns ns ns TIMING NAME Data Setup Data Hold PARAMETER tDSU tDH TYPICAL 52 14 UNITS ns ns
Write-Through Cycles
During startup and local register loading, any incoming writecycles to the Non-Volatile Memory will be held off until start up and configuration is complete. During normal operation, writes to the Non-Volatile Memory shall be extended until such time that the data is both written to and read back from the external EEPROM.
11
ISL6590 ISL6590 Data Write Protocol
5 clocks
CLK
5 clocks
8 Clocks
DATA
Start
Address: DeviceID
Address: Register
R/W
Dead Cycle
Ack (from ISL6580 )
Data Byte (to ISL6580)
Dead Cycle
Ack (from ISL6580 )
Stop
FIGURE 8. ISL6590 WRITE PROTOCOL
ISL6590 Data Read Protocol
5 clocks
SCLK
5 clocks
8 Clocks
SDATA
Start
Address: DeviceID
Address: Register
Ack Data Byte (from ISL6580) (from ISL6580 ) FIGURE 9. ISL6590 READ PROTOCOL
R/W
Dead Cycle
Dead Cycle
Ack (from ISL6580 )
Stop
12
ISL6590
ATX ARX
ASYNCHRONOUS SERIAL INTERFACE (ASI) DONE WRITE READ ADDR[15:0] DATA[7:0] MEMORY BUS MUX OPEN LOOP WRITE READ ADDR[15:0] DATA[7:0]
STATE CONTROL/ FAULT MONITOR
VID[5:0] OUTEN PWRGD
READ ADDR[15:0]
WRITE
DATA[7:0]
CONTROL AND STATUS REGISTERS
STATUS COEFFICIENTS CONTROL FEEDBACK CONTROL
EEPROM INTERFACE
MDI /MCS MCLK MDO
EEPROM INTERFACE
STATUS DONE ISL6580 MAPPED REGISTERS WRITE DEVICE[4:0] DATA[7:0] ADDR[4:0] MEMORY (REGISTERS) BACKSIDE SERIAL BUS
FIGURE 10. MEMORY INTERFACE DIAGRAM
Backside Serial Bus (BSB)
The transfer of data on the BSB consists of a start bit, 5 ID bits, 5 memory address bits, a read/write bit, an address acknowledge bit, 8 data bits, a data acknowledge bit, and a stop bit. The rate of transfer is set by the serial clock divider register. Background polling of ISL6580 fault registers is performed using the BSB. The fault information is written to the ISL6590 local copies of the ISL6580 fault registers. ISL6580 control registers can be written to or read back from the ISL6590 memory via the BSB.
repeated for each Power IC that may be in the system. This process is known as Device Polling. After this initial PWM polling is complete, the serial interface of each Power IC has to be configured with a device ID to be able to respond to serial commands later. This procedure involves issuing a "config call" which is to send a serial write command to global device ID `0'. During the data portion of the cycle, the Power IC to be configured has its PWM signal asserted by the Controller. This action allows the data bits that are sent from the Controller to be shifted into a device ID register within the Power IC. This process is known as Enumeration. During enumeration, the address on the serial bus for each ISL6580 is uniquely defined according to Table 6. If an address acknowledge bit is not returned, the device is not used because it is either not present or not functional. The PWM signals are used to enable address writing to each ISL6580. Fault processing is disabled during enumeration.
Startup Process
ISL6580 Enumeration
After power-up of the system, each installed ISL6580 is polled for its existence. This procedure involves the Controller to assert the PWM signal for a specific Power IC. If the specified Power IC is present, it will assert its signal to acknowledge seeing its PWM asserted. This sequence is
13
ISL6590
Address Cycle 10 clocks SCLK
Data Cycle 8 Clocks
Repeat for N-1 devices SDATA Start Configcall "0000000000" Ack R/W Directio n ID for Power IC 1 Ack Stop
PWM1 ("ID" register enable)
MHz Power IC 1 ID register enable
MHz Power IC Configuration Process First the master will initiate "config call" by sending a "10'h00" address All of the slaves should "ACK" because every MHz Power IC register contains 0" after reset The ID is then sent out during the data cycle. The process is repeated until all (N) of the devices are configured.
FIGURE 11. ENUMERATION TIMING DIAGRAM TABLE 10. SERIAL BUS ID MAPPING BSB ID 00h 01h 02h 03h 04h 05h 06h 09-1Fh "config call" Power IC 1 Power IC 2 Power IC 3 Power IC 4 Power IC 5 Power IC 6 Reserved DESCRIPTION
ISL6580 Softstart
The system is slowly brought out of the no output voltage open loop state by sending a small PWM pulse width to the ISl6580s. A fixed time period and step size is used to bring the output voltage into the lower range of the voltage ADC. Once the voltage ADC begins reading voltage, a fixed Vstep step size is used (25mV). After each Vstep step is performed, the output voltage must settle within a +/(Vstep/2) mV window of the specified VID voltage before stepping to the next output voltage setting. The stepping continues until the final voltage is reached.
Power On Reset
The ISL6590 controller performs a Power On Reset function internally. It holds all internal logic in a reset state until the Vdd (3.3V) exceeds a threshold. While in the reset state all PWM and NDRIVE signals are held at ground and all MOSFETs are OFF.
ISL6580 Calibration
Prior to calibration, the status of each ISL6580 is checked. The input supply voltage is checked by polling the status of the under-voltage lockout in the status registers of the ISL6580s. Other faults are also checked. If a fault is detected during or after calibration, the system state may be frozen while fault processing takes over to resolve the error. To calibrate the voltage ADC, the VID is set to the same voltage as the external VID setting. Voltage ADC calibration is initiated by setting the device that is hard wired for Regulation mode into calibration mode. This should be device #1. During calibration, any offset voltage internal to the ADC is output on the ERR serial line. The error is stored in the non-volatile memory. Then the ISL6590 changes themode of the ISL6580 to normal operation and calibration is complete. 14
Duty Cycle Limit
The ISL6590 limits the on time of the upper FETs. The system designer can set the maximum ON time with PowerCode software The value is put in as a percentage. If the duty cycle reaches this percentage, the top side FET turns off until the next cycle.
ISL6590
Loop Compensation
Any closed loop system must be designed to insure stability (prevent oscillation) and provide correct response to external events such as load transients. The output of a buck regulator has an inherent, low pass filter formed by the output inductor(s), output capacitance and their ESRs (Equivalent Series Resistance). Figure 12 shows a typical gain and phase plot of output inductors, capacitors and ESR.
0 -10 -20 Plant Gain (in DB) -30 -40 -50 -60 -70 -80 -90 1 10 100 Frequency (in KHz) 1000 -120 -140 10000 Plant Gain Phase 0 -20 Phase (in Degrees) -40 -60 -80 -100
FIGURE 13. TYPICAL ANALOG VOLTAGE LOOP BLOCK DIAGRAM
FIGURE 12. FREQUENCY RESPONSE OF THE OUTPUT INDUCTORS AND CAPACITORS
Above the resonant frequency of the output LC filter (10kHz in this case) the gain falls at a rate of 40dB/decade and the phase shift approaches -180 degrees. At a frequency above the F = 1/(2C*ESR) = 500kHz in this case) the gain slope changes to -20dB/decade and the phase shift approaches -90 degrees In a closed loop control system, the output is subtracted from a reference voltage to produce an error voltage. The error voltage is amplified and fed to the output stage. In a buck regulator the output stage consists of a Pulse Width Modulator (PWM), switching transistors (typically MOSFETs), series inductor(s) and output capacitors. High gain feedback reduces variation in the output due to changes in input voltage, load current and component values. However, high gain at high frequencies can cause excessive over shoot in response to transients ( if phase shift > 120 degrees and gain > 0dB ) or oscillation ( if phase shift > 180 degrees and gain > 0dB ). The trade off in designing the loop compensation is to achieve fast response to transients without excessive overshoot or oscillation.
FIGURE 14. DIGITAL CONTROL LOOP BLOCK DIAGRAM
The ISL6580 subtracts a reference from the output voltage to produce an error voltage. It converts the error voltage to a 6 bit digital number and sends it to the ISL6590 controller. The controller processes the error number numerically to provide gain (Proportional), phase lag (Integration) and phase lead (Derivative) functions. This forms the digital PID control.
FIGURE 15. TYPICAL ANALOG ERROR AMPLIFIER AND COMPENSATION
15
ISL6590
Adjusting The Digital PID
FIGURE 16. DIGITAL PID COMPENSATOR
Frequency response of the digital PID compensator is determined by the Kp, Ki, Kd factors. These factors are stored in nonvolatile memory and are loaded in the controller at power on reset. The system designer sets the PID compensators frequency response using user interface software. The designer enters the frequencies of the desired poles and zeros and user interface software calculates the Kp, Ki and Kd factors. the software will calculate and display the frequency response of the feedback and the closed loop system.
FIGURE 18. SMALL SIGNAL DESIGN WINDOW
FIGURE 19. BODE PLOT
FZ1 = Frequency of first zero FZ2 = Frequency of second zero FP0 = Gain * frequency of first pole (A DC*F P0) FP1 = Frequency of second pole
FIGURE 17. DESIGN PARAMETER INPUT WINDOW
RP2 = External Resistor used for third pole CP2 = External Capacitor used for third pole FP2 = 1 / (2 * * RP2 * CP2 ) The software will calculate the frequency response of the PID controller and the closed loop system as in figures 20 and 21 below.
16
Primarion is a registered trademark of Primarion, Inc. Primarion PowerCode is a trademark of Primarion, Inc
ISL6590
60 50 Feedback Gain (in DB) 40 30 20 10 0 1 10 100 Frequency (in KHz) 1000 Compensation Phase 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 10000 Phase (in Degrees)
slightly below 180 degrees at the cross over frequency, the loop will respond to transients with overshoot and ringing. Loop phase shift between 90 and 120 degrees at the cross over frequency (Phase margin = 60 to 90 degrees) results in little or no over shoot and ringing. Large phase margins (>90 degrees) result in slower transient response.
Time Domain
It is recommended to place the first zero (FZ1) at the resonant frequency of the output inductors and capacitors (F = 1/(2LC = 10kHz in this case). Then increase FZ2 and FP0 to minimize response time over (under) shoot and ringing. The first microseconds of transient response are primarily dependant on the ESR and ESL of the output capacitors. After the affects of ESL and ESR pass the loop must control the response.
FIGURE 20. PID COMPENSATOR FREQUENCY RESPONSE
60 40 20 Loop Gain (in DB) 0 -20 -40 -60 -80 -100 -120 1 10 100 Frequency (in KHz) 1000 Loop Phase 400 350 300 250 200 150 100 50 0 -50 10000 Phase (in Degrees)
FIGURE 21. FREQUENCY RESPONSE OF THE CLOSED LOOP
Compensation Methodology
Due to the user interface software interface, it is very easy to change the frequency compensation and see the resulting performance on a scope or network analyzer. Transient response is viewed by applying a transient load and monitoring the output voltage with a scope. Frequency response is viewed by placing a small resistor between the output and the feed back network, applying a small sine wave at the input to the feed back network and measuring the amplitude and phase shift of the resulting sine wave on the output. Sweeping the frequency produces plots similar to those above.
FIGURE 22. TYPICAL RESPONSE TO A LOAD TRANSIENT
User Interface Software
The ISL6590 controller and the ISL6580 intelligent power stage have programmable values that can be changed using the User Interface Software. The loop configuration and system performance is adjusted using the software. The use of the software allows the engineer to evaluate the system performance without having to physically change components on the board. Primarion PowerCode user interface software (provided by Intersil and our partner Primarion). Below are screen shots showing data entry points, pull down menus, buttons for help and a tutorial. The user interface software allows the designer to adjust the load line, frequency response, ATR and protection modes.
Frequency Domain
It is recommended to place the first zero (FZ1) at the resonant frequency of the output inductors and capacitors (F = 1/(2LC) = 10kHz in this case). Then increase FZ2 and FP0 to maximize DC gain and the frequency at which gain drops below 0dB while keeping the phase margin above 60 degrees. Phase Margin is the difference between 180 degrees and the phase shift of the loop at the frequency where the gain drops below 0dB (cross over frequency). If the loops phase shift reaches 180 degrees and has gain equal to or greater than 0dB, it acts as positive feed back and the loop will oscillate. Even if the loops phase shift is 17
ISL6590
FIGURE 23. PRIMARION POWERCODE LOADLINE AND ATR SETTINGS
FIGURE 25. PRIMARION POWERCODE MONITOR WINDOW
FIGURE 24. PRIMARION POWERCODE LOOP RESPONSE SETTINGS
FIGURE 26. PRIMARION POWERCODE DESIGN INPUTS
FIGURE 27. PRIMARION POWERCODE DUTY CYCLE LIMIT SELECTION
18
ISL6590 Register Description Tables
TABLE 11. ISL6590 MEMORY MAP ADDRESS RANGE VOLATILE MEMORY 0000 - 01FF 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 - 00EF 00F0 00F1 - 00FF 0100 - 01FF 0200 - 02FF 0200 0201 0202 0203 0204 - 0205 0206 0207 0208 209 General Control Registers Part Number (ASCII character #1) Part Number (ASCII character #2) Part Number (ASCII character #3) Part Number (ASCII character #4) Version Number (ASCII) Vendor Name (ASCII character #1) Vendor Name (ASCII character #2) Vendor Name (ASCII character #3) Vendor Name (ASCII character #4) Reserved SPI Memory Status Register Reserved Serial Polling Enable Reserved System Status (LSB) System Status (MSB) Oscillator-In Frequency (LSB) Oscillator-In Frequency (MSB) State Control Status (LSB) State Control Status (MSB) Reserved Reserved Reserved Scratchpad Reserved Reserved Control/Status Registers Reserved Feedback Loop Control Open Loop PID (LSB) Open Loop PID (MSB) Reserved ATR Control Phases Used Phase Enables Reserved
R/W R R/W 4 4 8
NAME
R/W/S (NOTE 1)
SIZE (BITS)
R/W/Ws1 SIZE (bits) R R R R R R R R R 8 8 8 8 8 8 8 8 8
R
3
R/W
1
R/Ws R/Ws R R R/Ws R/Ws
8 8 8 8 8 8
R/W
8
R/W/Ws1 Size (bits)
R/W R/W R/W
6 8 7
19
ISL6590
TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE 020A 020B 020D 020E 020F 0210 0211 0212 0213 0214 0215 0216 0217 0218 0219 021A 021B 021C - 21F 0220 0221 0222 0223 0224 0225 0226 0227 0228 - 022F 0230 0231 0232 0233 0234 0235 0236 0237 0238 - 02FF 0300 - 03FF 0400 - 07FF 0400 VID_IN_SOFT Alive Found Reserved VCODE_IN VCODE_OUT Enumeration Control Enumeration Done VID_IN (from VID pins) OUTEN (from OUTEN pin) PWRGD VID_OUT Voltage Error Average Peak Channel Current Overload AVP Offset Voltage Calibration Offset Regulated Reserved Peak Channel Current - Phase 1 Peak Channel Current - Phase 2 Peak Channel Current - Phase 3 Peak Channel Current - Phase 4 Peak Channel Current - Phase 5 Peak Channel Current - Phase 6 Peak Channel Current - Phase 7 Peak Channel Current - Phase 8 Reserved On Time - Phase 1 (upper 8 bits) On Time - Phase 2 (upper 8 bits) On Time - Phase 3 (upper 8 bits) On Time - Phase 4 (upper 8 bits) On Time - Phase 5 (upper 8 bits) On Time - Phase 6 (upper 8 bits) On Time - Phase 7 (upper 8 bits) On Time - Phase 8 (upper 8 bits) Reserved Reserved Broadcast Write Memory Map Reserved R/W/Ws1 Size (bits) R R R R R R R R 8 8 8 8 8 8 8 8 R R R R R R R R 6 6 6 6 6 6 6 6 R R/W R/W R R R R R R R R R R/W R 8 8 3 4 6 1 1 7 6 6 8 8 5 1 NAME R/W/S (NOTE 1) R/W R SIZE (BITS) 6 8
20
ISL6590
TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE 0401 0402 0403 0404 0405 0406 0407 0408 0409 040A 040B 040C 040D - 041F Reserved HFWND (High ATR Window) LFWND (Low ATR Window) VID (7 bit Voltage Identification) ILIM (Current Limit) TSD (Thermal Shutdown) Reserved TEST ENABLE1 (Block Enables LSB) ENABLE2 (Block Enables MSB) SPARE1 SPARE2 Reserved Device 1 Memory Map 0420 0421 0422 0423 0424 0425 0426 0427 0428 0429 042A 042B 042C 0440 - 07FF Reserved Bus ID HFWND (High ATR Window) LFWND (Low ATR Window) VID (7 bit Voltage Identification) ILIM (Current Limit) TSD (Thermal Shutdown) FAULT (Fault Status) TEST ENABLE1 (Block Enables LSB) ENABLE2 (Block Enables MSB) SPARE1 SPARE2 Device n to 31 Memory Map (structure as Device 1) R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W 4 4 4 7 2 3 6 8 8 3 8 8 R/W/Ws1 SIZE (bits) W W W W W 8 8 3 8 8 W W W W W 4 4 7 2 3 NAME R/W/S (NOTE 1) SIZE (BITS)
NON-VOLATILE MEMORY 0800 - 09FF 0800 0801 0802 0803 0804 0805 0806 0807 0808 General Settings NVMEMCODE Serial Clock Divider VID_IN Table Select VID_OUT Table Select OffOn Non-Overlap Driver Control OnOff Non-Overlap Driver Control Duty Limit System Configuration Reserved R/W/Ws1 Size (bits) R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 3 2 2 4 4 8 3 5
21
ISL6590
TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE 0809 080A 080B 080C 080D 080E 080F 0810 0811 0812 0813 0814 0815 0816 0817 0818 0819 081A 081B 081C 081D 081E - 083F 0840 0841 0842 0843 0844 - 086F 0870 - 08FF Address Range A/D ID WCOMP ID OUVP ID MG Poll Priority State Control Reserved Phases to be Used POR Wait Regulation Window Regulation Time Voltage Calibration Maximum Reserved Startup Fault Mask Startup Enables 1 Startup Enables 2 Active Fault Mask Active Enables 1 Active Enables 2 Active Feature Mask Reserved Current Limit Reserved ATR Exit Delay ATR Count Max (LSB) ATR Count Max (MSB) PVID Offset Reserved Reserved General Control Registers R/W/Ws1 Size (bits) R/W R/W R/W R/W 5 8 1 4 R/W 6 NAME R/W/S (NOTE 1) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SIZE (BITS) 5 5 5 7 6 2 8 5 6 8 6 8 7 8 5 7 8 5 1
Phase # Independent Compensation Parameters 0900 0901 0902 0903 0904 0905 0906 0907 0908 Kp AVP Kd AVP Kp PID Ki PID Kd Transient Recovery Vos AVP Ios AVP Kfp PID Kfd PID R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 6 8 8 6 8 6 6
22
ISL6590
TABLE 11. ISL6590 MEMORY MAP (Continued) ADDRESS RANGE Phase # Dependent Compensation Parameters 0909 090A 090B 090C 090D 090E 090F 0910 0911 0912 0913 0914 0915 0916 0917 0918 0919 091A 091B 091C 091D 091E 091F 0920 0921 0922 - 093F 0940 0941 - 097F 0980 - 09FF 0A00 - FFFF K Current Balancing Kd PID HFWND LFWND OUVPLF OOVPHF ILIM (not phase # dependent) Reserved Reserved Switching Frequency Phases=1 (LSB) Switching Frequency Phases=1 (MSB) Switching Frequency Phases=2 (LSB) Switching Frequency Phases=2 (MSB) Switching Frequency Phases=3 (LSB) Switching Frequency Phases=3 (MSB) Switching Frequency Phases=4 (LSB) Switching Frequency Phases=4 (MSB) Switching Frequency Phases=5 (LSB) Switching Frequency Phases=5 (MSB) Switching Frequency Phases=6 (LSB) Switching Frequency Phases=6 (MSB) Switching Frequency Phases=7 (LSB) Switching Frequency Phases=7 (MSB) Switching Frequency Phases=7 (LSB) Switching Frequency Phases=7 (MSB) Reserved Custom VID2VCODE0 LUT Entry Custom VID2VCODE1 to VID2VCODE63 LUT Entries Reserved for User Reserved
R/W R/W 8 8
NAME
R/W/S (NOTE 1)
SIZE (BITS)
R/W R/W R/W R/W R/W R/W R/W
8 8 4 4 4 4 2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4
R/W/Ws1 SIZE (bits)
TABLE 12. SECOND SOURCE INFORMATION PART NUMBER Primarion PX3530 TEMP. (oC) 0 to 85 PACKAGE 64 Ld QFN PKG. NO L64.9x9
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 23
ISL6590 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L64.9x9-S
64 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL
2X
0.10 A 9 D1
N
MIN 0.70 -
NOMINAL 0.75 0.50 0.25 REF
MAX 0.80 0.05 -
NOTES -
A
C A
D D/2
A1 A2
D1/2
2X
0.10 C B
A3 b 0.18
6
INDEX 1 AREA 2 3
0.20 9.00 BSC 8.75 BSC
0.30
5, 8 -
E1/2
E/2
D D1
E1 9
E
D2 E E1 E2
3.64
3.74 9.00 BSC 8.75 BSC
3.84
7, 8 -
3.64
3.74 0.50 BSC
3.84
7, 8 -
0.10
C
B B TOP VIEW
e
C A
2X
0.10
k L
0.25 0.30 -
0.40 64 16 16
0.50 0.15
8 9 2 3 3
2X
4X 0
A2
A
L1
// 0.10 C C 0.08
N Nd Ne
SEATING PLANE
C
SIDE VIEW
A3
A1
5 4X b
0.10
M
CA B
P
-
-
0.50 8
Rev. 0 04/03
7 4X P (DATUM B) D2 D2 2
8
NX k N
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees.
E2 (Ne-1)Xe REF.
4X P
(DATUM A)
6 INDEX AREA
3 2 1
E2/2
5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
7
8
NX L
N e (Nd-1)Xe REF.
BOTTOM VIEW
A1 NX b 5
9. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
SECTION "C-C"
SCALE: NONE
C L
9 e TERMINAL TIP
L L1
FOR EVEN TERMINAL/SIDE
24

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